Make command usually write in Makefile.
Makefile syntax
Makefile construct by rules.
# rule
<target> : [prerequisites]
<commands>
target
One or more file name, and the operator(phony target) is okay.
clean:
rm *.o
This is a phony target, but when the file clean exist, make clean will not effect.
To avoid this phenomenon, we can declare clean as the phony.
.PHONY: clean
clean:
rm *.o temp
[prerequisites]
example:
result: source
cp source result
command
shell command.
Every line of command execute in different terminal.
But you can solve in three ways.
Use
;as end of a command and write other command in the same line.Use
;and add\before other line.Add the target
.ONESHELL:
other syntax
echoing
Make will print each command, and add @ before each line can close the echoing.
Usually, we will add @ before #.
wildcard *
*: all words
?: one word
...: all sub directory
match *
% can match some part of file name
%.o: %.c
variable *
vars = loomt dakta
show-vars:
echo $(vars) @# makefile变量
echo $$HOME @# Shell变量
VARIABLE = value # 在执行时扩展，允许递归扩展。
VARIABLE := value # 在定义时扩展。
VARIABLE ?= value # 只有在该变量为空时才设置值。
VARIABLE += value # 将值追加到变量的尾端。
implicit variables *
$(CXX) -o a a.c
automatic variables *
$@: self target
$<: first prerequisite
$^: all prerequisites
for *
LIST = one two three
for-test:
for i in $(LIST);\
do echo $$i;\
done
for i in $$(seq 1 10) ; do \
echo "iterator $$i"; \
done
if *
without tab
if-test:
ifeq (g++,$(CXX))
echo "cxx eq g++"
else
echo "cxx neq g++"
endif
function *
Shell
goenv := $(shell go env)
shell-test:
echo $(goenv)
Wildcard
path-files := $(wildcard ./*)
wildcard-test:
echo $(path-files)
Subst
comma:= ,
empty:=
# space变量用两个空变量作为标识符，当中是一个空格
space:= $(empty) $(empty)
foo:= a b c
bar:= $(subst $(space),$(comma),$(foo))
# bar is now `a,b,c'.
subst-test:
echo $(bar)
Patsubst
patsubst-test:
echo $(patsubst dakta%,loomt_%,dakta@example.com)
reference: