Make command usually write in Makefile.
Makefile syntax
Makefile construct by rules.
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target
One or more file name, and the operator(phony target) is okay.
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This is a phony target, but when the file clean exist, make clean will not effect.
To avoid this phenomenon, we can declare clean as the phony.
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[prerequisites]
example:
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command
shell command.
Every line of command execute in different terminal.
But you can solve in three ways.
-
Use
;as end of a command and write other command in the same line. -
Use
;and add\before other line. -
Add the target
.ONESHELL:
other syntax
echoing
Make will print each command, and add @ before each line can close the echoing.
Usually, we will add @ before #.
wildcard *
*: all words
?: one word
...: all sub directory
match *
% can match some part of file name
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variable *
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VARIABLE = value # 在执行时扩展,允许递归扩展。
VARIABLE := value # 在定义时扩展。
VARIABLE ?= value # 只有在该变量为空时才设置值。
VARIABLE += value # 将值追加到变量的尾端。
implicit variables *
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automatic variables *
$@: self target
$<: first prerequisite
$^: all prerequisites
for *
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if *
without tab
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function *
Shell
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Wildcard
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Subst
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Pastsubst
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reference: